The design of highly integrated circuits follows a path from an abstract description of the integrated circuit, for instance in a hardware description language such as VHDL, to a physical layout. The physical layout defines geometrical parameters of device elements of the integrated circuit. The device elements may be defined by polygon-based structures to be fabricated on a wafer.
The wafer fabrication comprises lithographic steps, in which the physical layout is fabricated layer by layer using a respective lithographic mask. The mask layout is printed to a photosensitive resist layer deposited temporarily on the wafer. As a part of the lithographic printing process, the resist layer is exposed through the mask and developed to expose sections of a wafer, which are to be processed by etching or material deposition. After the respective required processing, the resist is removed, and a next lithographic step can be performed.
With increasing integration densities of integrated circuits the lithographic generation of a physical layout on a wafer has become more and more challenging. One reason is the continuing reduction of lateral feature extensions in the physical layout. Another reason is a diminishing of process windows that can be used during the lithographic process. A process window is spanned by allowable values of a dose of exposure-radiation used for exposing the resist layer and by a focused position of a mask-image plane relative to the resist layer in a depth direction of the resist layer.
Generally the mask design involves a process called design rule check (DRC), in which the physical layout is verified and corrected, if necessary. Only after proper DRC processing, the physical layout is used for fabricating the masks for different layers of the integrated circuit, which are going to be used during wafer fabrication. To cope with the increased challenges of high integration densities, the mask design process has been extended by techniques such as Optical Proximity Correction (OPC), Mask Rule Checking (MRC) and Optical Rule Checking (ORC). During the OPC flow, the mask design is changed using a physical model to assess process printing characteristics. The physical model is composed of an optical model and a resist model. The optical model takes account of the physical effects influencing the formation of an aerial image of the mask. The resist model takes account of the characteristics of the resist layer in the formation of the real image of the mask during the exposure and in the development after exposure. These two components of the OPC model enable a rapid calculation of the intensity of an aerial image and of the resist contour during the flow of the OPC method.
To detect potential printing failures across the process window, one solution is a calibration of an optical model and of a resist model from experimental data obtained from fabricated test prints of test patterns. Subsequently, the printing contours of the test patterns in the test prints are simulated at several points of the process window and the lateral extensions of the simulated patterns are measured. However, this technique requires much computing run time.
An alternative solution is the use of a so-called critical-failure ORC (CFORC) technique. CFORC is described in the publication 1. Belledent et al., “Critical failure ORC—Application to the 90-nm and 65-nm nodes.” Optical Microlithography XVII, ed. Bruce W. Smith, Proceedings of SPIE Vol. 5377 (SPIE, Bellingham, Wash., 2004), pp. 1184 to 1197. CFORC uses an empirical formula that links a simulated aerial image to a likelihood of any feature to fail within the process window requirements. The calibration is based on experimental data using the full process flow and full process window of a layer being characterized. It allows for instance capturing pinching and bridging effects on a layer of polysilicon.
A process flow that is used to calibrate a critical-failure model in the CFORC process flow is described in this article. In a first processing step, test patterns are designed and fabricated using commonly known processes involving the fabrication of a mask and the printing of the mask pattern by lithographic steps on a wafer. The experimental results are collected from throughout the process window to also cover ranges of printing failure. A printing feature will be flagged if it fails to be well patterned at any process condition. After performing the measurements, aerial images are collected at best printing conditions using an optical model that is calibrated on data based on successful printing. In that way, the aerial image shape and failing status are gathered in a text file. The aerial image is characterized by a set of optical parameters. The optical parameters can for example be a minimum intensity, a maximum intensity, and a slope at a predefined reference threshold intensity that corresponds to the onset of printing in an intensity contour across a printing feature. A classification is then performed on the basis of pass-fail data obtained form exploring the process window in step 106 and from the optical parameters obtained. The classification serves to find a boundary between two or more different categories of the experimental of the rations, which are for examples “pass” or “fail”. A failure model or classification boundary is described in the formclass(x)=c1*kernel(x−x1)+c2*kernel(x−x2)+ . . . ,where x is a vector of input parameters, x1, x2 are observation points, and “kernel” describes a Gaussian kernel. The observation points x1, x2 . . . are the optical parameters and pass/fail observations of each feature in the test patterns. A boundary between pass and fail regions is calculated on the basis of this classification, which forms the CFORC model. The CFORC model can be used to take features in a physical layout during simulation to indicate their likelihood to fail during printing.
It would be desirable to use a method for calibrating a critical-failure model that needs less processing expenditure.